The present invention relates to a semiconductor device in which memory and logic circuits are formed on a single semiconductor chip.
In a semiconductor device in which memories such as DRAM's are integrated on a semiconductor chip, a larger number of sense amplifier circuits, placed adjacent to an array of memory cells, are activated simultaneously during a read or write operation. Accordingly, large instantaneous current flows through peripheral circuits for the sense amplifier circuits or sense amplifier driver circuits driving these sense amplifier circuits, and the ground level of the array of memory cells varies. As a result, the access time possibly increases.
In order to prevent such an increase in access time and stabilize the operation of memories, various measures have heretofore been taken. For example, the contact of the peripheral circuits for the sense amplifier circuits with a ground is stabilized. The energy of alpha rays is attenuated by coating an array of memory cells with a silicone resin or the like. or an error correction circuit is introduced into an array of memory cells.
In recent years, a semiconductor device, in which large-capacity memory circuits such as DRAM's (hereinafter, referred to as a "memory section" collectively) and custom logic circuits like CPU's and ASIC's (hereinafter, referred to as a "logic section" collectively) are integrated on a single semiconductor chip, has already been implemented.
Accordingly, such a semiconductor device in which memory and logic sections are integrated on a single semiconductor chip poses a new problem that the logic section might be adversely affected in various manners by the memory section.
Firstly, a variation in ground level of the array of memory cells in the memory section might have an unwanted effect on some circuits in the logic section, e.g., circuits performing an analog operation, in particular.
Secondly, such a semiconductor device having memory and logic sections integrated on a single chip is more expensive to manufacture. The reason is as follows: since such a semiconductor device takes on a custom-made nature more often than not, bigger packages are frequently used therefor. Accordingly, when a technique of preventing soft errors by increasing the purity of a package resin or by coating the surface of the chip is employed, higher costs are required for bigger packages.
Thirdly, in accordance with currently available techniques, a freely usable space, existing over the memory section, cannot be fully taken advantage of. Specifically, in a semiconductor device having memory and logic sections integrated on a single semiconductor chip, the memory section occupies about a half of the entire area of the semiconductor chip. Thus, a space where interconnects can be disposed exists over the memory section. However, if interconnects are disposed over the memory section, then memory cells or bit lines might possibly receive noise from the upper-level interconnects. Accordingly, even though such a space where interconnects can be disposed exists over the memory section, the space cannot be utilized effectively. This is because signal lines, which are usually more likely to generate noise, should not constitute an upper-level interconnect layer over the memory section.
Furthermore, although the operating speed of semiconductor devices included in an electronic device has recently been increased in general, electromagnetic wave noise emitted from such an electronic device has tended to increase. Accordingly, a problem of bidirectional electromagnetic interference arises. Specifically, the electromagnetic wave noise, emitted from an electronic device, adversely affects other appliances or parts due to radiation or electromagnetic induction, while the electronic device itself experiences the harmful effects of externally incoming electromagnetic wave noise. Thus, suppressing electromagnetic wave noise and electromagnetic interference as much as possible is a common important problem to be solved for electronic devices of every sort, as well as semiconductor devices having memory and logic sections integrated on a single chip.